View HI-3596PSIF-40_7001177.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

holt integrated circuits www.holtic.com 1 january, 2012 hi-3596, hi-3597, hi-3598, hi-3599 octal arinc 429 receivers with label recognition and spi interface ds3598 rev. c 01/12 ? 32 nd bit can be data or parity ? low power ? industrial & extended temperature ranges pin configuration (top view) ( see page 13 for additional package pin confgurations ) general description the hi-359x family from holt integrated circuits are sili - con gate cmos ics for interfacing up to eight arinc 429 receive buses to a high-speed serial peripheral interface (spi) enabled microcontroller. each receiver has user-programmable label recognition for up to 16 labels, a four-word data buffer (fifo), and an on-chip analog line receiver. receive fifo status can be moni - tored using the programmable external interrupt pins, or by polling the status register. other features include the ability to switch the bit-signifance of the arinc 429 label and to recognize the 32 nd received arinc bit as either data or a parity fag. some versions provide a digi - tal transmit channel which can be utilized with an exter - nal line driver such as hi-8570 to relay information from multiple sources, for example sensors, to a single col - lection point such as a fight computer and can also be confgured as a loopback test register for each receive channel. versions are also available with different input resistance values to provide fexibility when using exter - nal lightning protection circuitry. the spi and all control signals are cmos and ttl compatible and support 3.3v or 5v operation. the hi-3596 and hi-3598 are full featured parts. the hi-3597 and hi-3599 give the user the option of utilizing a smaller 24-pin soic package with very little trade off in features. in this case, a global interrupt fag is provided instead of individual external fifo interrupt pins. the hi-3597 is identical to the hi-3599 except that it offers the digital transmit feature and seven receive channels. features ? arinc 429 compliant ? up to 8 independent receive channels ? digital transmit channel (except hi-3599) ? 3.3v or 5.0v logic supply operation ? on-chip analog line receivers connect directly to arinc 429 bus ? programmable label recognition for 16 labels per channel ? independent data rate selection for each receiver ? four-wire spi interface ? label bit-order control 52 - flag1 51 - flag2 50 - flag3 49 - flag4 48 - flag5 47 - flag6 46 - flag7 45 - flag8 44 - vdd 43 - flag 42 - rin8b 41 - rin8b-40 40 - rin8a-40 39 - rin8a 38 - rin7b 37 - rin7b-40 36 - rin7a-40 35 - rin7a 34 - rin6b 33 - rin6b-40 32 - rin6a-40 31 - rin6a 30 - rin5b 29 - rin5b-40 28 - rin5a-40 27 - rin5a rin2a - 14 rin2a-40 - 15 rin2b-40 - 16 rin2b - 17 rin3a - 18 rin3a-40 - 19 rin3b-40 - 20 rin3b - 21 gnd - 22 rin4a - 23 rin4a-40 - 24 rin4b-40 - 25 rin4b - 26 aclk - 1 sck - 2 si - 4 so - 5 mr - 6 tx1 - 7 tx0 - 8 rin1a - 9 rin1a-40 - 10 rin1b-40 - 11 rin1b - 12 - 13 hi-3598pqi & hi-3598pqt cs - 3 __ hi-3598 full function, full pin-out version 52 - pin plastic quad flat pack (pqfp) aclk - 1 sck - 2 si - 4 so - 5 tx1 - 6 tx0 - 7 rin2a - 8 rin2b - 9 rin3a - 10 rin3b - 11 gnd - 12 cs - 3 24 - vdd 23 - flag 22 - rin8b 21 - rin8a 20 - rin7b 19 - rin7a 18 - rin6b 17 - rin6a 16 - rin5b 15 - rin5a 14 - rin4b 13 - rin4a hi-3597 psi & hi-3597 pst hi-3597 minimum footprint, reduced pin-out version 24 - pin plastic small outline package (soic)
hi-3596, hi-3597, hi-3598, hi-3599 holt integrated circuits 2 block diagrams rin1a rin1b sck cs si so aclk gnd 40 kohm 40 kohm rin1a-40 rin1b-40 flag1 flag2 flag3 flag4 flag5 flag6 flag8 flag { mr flag7 hi-3596 & hi-3598 spi interface tx1, tx0 channel 1 ch 8 ch 7 ch 6 ch 4 ch 3 ch 2 ch 5 transmit register vdd status register arinc 429 bus 1 bus 2 control register bus 3 bus 4 bus 5 bus 6 bus 7 bus 8 arinc 429 valid word checker arinc 429 line receiver arinc 429 received data fifo (4 words) label filter 16 label filter memory note: rin1a & rin1b available only on hi-3596 rin1a-40 & rin1b-40 available only on hi-3596-40 tx1, tx0 (hi-3597 only) *note: rin1a & rin1b are not available on hi-3597 vdd spi interface status register arinc 429 received data fifo (4 words) label filter arinc 429 valid word checker arinc 429 line receiver 16 label filter memory rin1a* rin1b* sck cs si so aclk gnd 40 kohm 40 kohm channel 1 ch 8 ch 7 ch 6 ch 4 ch 3 ch 2 ch 5 arinc 429 bus 1 flag { hi-3597 & hi-3599 (24-pin versions) bus 2 control register transmit register the 40 kohm resistors are shorted on the hi-3597-40 and hi-3599-40 bus 3 bus 4 bus 5 bus 6 bus 7 bus 8 figure 1. block diagrams
hi-3596, hi-3597, hi-3598, hi-3599 holt integrated circuits 3 pin descriptions table 1. pin descriptions pin function description 3596 3597 3598 3599 vdd power 3.3v or 5.0v power supply x x x x gnd power chip 0v supply x x x x cs input chip select. data is shifted into si and out of so when cs is low x x x x sck input spi clock. data is shifted into or out of the spi interface using sck x x x x si input spi interface serial data input x x x x so output spi interface serial data output x x x x aclk input master 1 mhz timing reference for the arinc 429 receiver and transmitter x x x x rin1a* - rin8a arinc input arinc receiver positive input. direct connection to arinc 429 bus std std x std rin1b* - rin8b arinc input arinc receiver negative input. direct connection to arinc 429 bus std std x std rin1a-40* - rin8a-40 arinc input alternate arinc receiver positive input. requires external 40k resistor -40 -40 x -40 rin1b-40* - rin8b-40 arinc input alternate arinc receiver negative input. requires external 40k resistor -40 -40 x -40 flag1 - flag8 output goes high when arinc 429 receiver fifo is not empty (cr1=0), or full (cr1=1) x - x - flag output logical or of flag1 through flag8 x x x x tx1 output arinc 429 test word one state serial output pin x x x - tx0 output arinc 429 test word zero state serial output pin x x x - mr input hardware active high master reset. clears all receivers and fifos. does not affect control register contents. x - x - * note: rin1a & rin1b are not available on hi-3597
hi-3596, hi-3597, hi-3598, hi-3599 holt integrated circuits 4 table 2. defned instructions arinc channel op code hex data field description x 0h none instruction not implemented. no operation. 1h - 8h 1h 128 bits load label values to label memory. the data feld consists of 16, 8-bit labels. if fewer than 16 labels are needed for the application, the memory must be padded with redundant (duplicate) label values. 1h - 8h 2h 128 bits read the contents of the label memory for this channel. 1h - 8h 3h 32 bits read an arinc word from the receive fifo for this channel. if the fifo is empty all zeros will be read. 1h - 8h 4h 16 bits load the specifed channels control register and clear that channels fifo. 1h - 8h 5h 16 bits read the specifed channels control register. x 6h 16 bits read the status register. x 7h none master reset (all channels). x 8h 32 bits load the transmit register (high-speed data rate). this can also be used as a test word for each receiver (loopback self-test). x 9h 32 bits load the transmit register (low-speed data rate). this can also be used as a test word for each receiver (loopback self-test). x ah - fh none instruction not implemented. no operation. instructions instruction op codes are used to read, write and con - fgure the hi-359x devices. the instruction format is illustrated in figure 2. when cs goes low, the next 8 clocks at the sck pin shift an instruction op code into the decoder, starting with the frst rising edge. the op code is fed into the si pin, most signifcant bit frst. for write instructions, the most signifcant bit of the data word must immediately follow the instruction op code and is clocked into its register on the next rising sck edge. data word length varies depending on word type written: 16-bit control register writes, 32-bit transmit register writes or 128-bit writes to a channels label- matching enable/disable memory. for read instructions, the most signifcant bit of the requested data word appears at the so pin after the last op code bit is clocked into the decoder, at the next fall - ing sck edge. as in write instructions, the data feld bit-length varies with read instruction type. channel-specifc instructions use the upper four bits to specify an arinc 429 receiver channel, 1-8 hex. the lower four bits specify the op code, described in table 2. the four channel assignment bits are dont care for instructions that are not channel-specifc, such as mas - ter reset. example: one spi instruction op code 14 hex data field 0232 hex msb lsb msb ls b cs sck si spi instruction format 7 6 5 4 3 2 1 0 msb lsb arinc 429 channel op code ie: load channel 1 control register with 0232 hex figure 2. spi instruction format
hi-3596, hi-3597, hi-3598, hi-3599 holt integrated circuits 5 functional description control word register each hi-359x receive channel is assigned a 16-bit control register which confgures that receiver. con - trol register bits cr15 - cr0 are loaded from a 16-bit data value appended to spi instruction n4 hex, where n is the channel number 1-8 hex. writing to the con - trol register also clears the data fifo for that channel. the control register contents may be read using spi instruction n5 hex. table 3 summarizes the control reg - ister bits functions. table 3. control register bits functions cr bit function state description cr0 (lsb) receiver data rate select 0 data rate = aclk/10 (arinc 429 high-speed) 1 data rate = aclk/80 (arinc 429 low-speed) cr1 rflag defnition 0 flag goes high when receive fifo is not empty (contains at least one word) 1 flag goes high when receive fifo is full cr2 enable label recognition 0 label recognition disabled 1 label recognition enabled cr3 reset receiver 0 normal operation 1 reset this receiver (clear receiver logic and fifo). the receive channel is disabled if cr3 is left high cr4 receiver parity check enable 0 receiver parity check disabled 1 receiver odd parity check enabled cr5 self-test (loopback) 0 receivers inputs are connected to the transmit register serial data output. 1 normal operation cr6 receiver decoder 0 receiver decoder disabled 1 arinc bits 10 and 9 must match cr7 and cr8 cr7 - - if receiver decoder is enabled, the arinc bit 10 must match this bit cr8 - - if receiver decoder is enabled, the arinc bit 9 must match this bit cr9 arinc label bit order 0 label bit order reversed (see table 5) 1 label bit order same as received (see table 5) cr10 to cr15 (msb) not used x control register read returns 0 for these bits status register the hi-359x devices have a single 16-bit status reg - ister which is read to determine status for the eight received data fifos. the status register is read using spi instruction n6 hex. table 4 summarizes the status register bits functions. table 4. status register bits functions cr bit function state description sr0 (lsb) receiver 1 fifo empty 0 receiver 1 fifo contains valid data. resets to zero when all data has been read. flag pin refects the state of this bit when cr1=0 1 receiver 1 fifo is empty sr1 receiver 2 fifo empty 0 receiver 2 fifo contains valid data. 1 receiver 2 fifo is empty sr2 to sr6 receiver 3 to receiver 7 fifo empty : : : : : : : : sr7 receiver 8 fifo empty 0 receiver 8 fifo contains valid data. 1 receiver 8 fifo is empty sr8 receiver 1 fifo full 0 receiver 1 fifo not full. flag pin refects the state of this bit when cr1=1 1 receiver 1 fifo full. to avoid data loss, the fifo must be read within one arinc word period. sr9 receiver 2 fifo full 0 receiver 2 fifo not full. 1 receiver 2 fifo full. sr10 to sr14 receiver 3 to receiver 7 fifo full : : : : : : : : sr15 (msb) receiver 8 fifo full 0 receiver 8 fifo not full. 1 receiver 8 fifo full.
hi-3596, hi-3597, hi-3598, hi-3599 holt integrated circuits 6 arinc 429 data format control register bit cr9 controls how individual bits in the received arinc word are mapped to the hi-359x spi data word during data read operations. table 5 describes this mapping. table 5. spi / arinc bit-mapping spi / arinc bit-mapping spi order 1 2 - 22 23 24 25 26 27 28 29 30 31 32 arinc bit 32 31 - 11 10 9 1 2 3 4 5 6 7 8 cr9 = 0 parity data sdi sdi label (msb) label label label label label label label (lsb) arinc bit 32 31 - 11 10 9 8 7 6 5 4 3 2 1 cr9 = 1 parity data sdi sdi label (lsb) label label label label label label label (msb) arinc 429 receiver arinc bus interface figure 3 shows the input circuit for each on-chip arinc 429 line receiver. the arinc 429 specifcation requires detection levels summarized in table 6. table 6. arinc 429 detection levels state differential voltage one +6.5 volts to +13 volts null +2.5 volts to -2.5 volts zero -6.5 volts to -13 volts differential amplifiers comparators rina-40 rina rinb rinb-40 vdd gnd vdd gnd one nul l zero figure 3. arinc receiver input the hi-359x family guarantees recognition of these lev - els with a common mode voltage with respect to gnd less than 30v for the worst case condition (3.15v sup - ply and 13v signal level). the tolerances in the design guarantee detection of the above levels, so the actual acceptance ranges are slightly larger. if the arinc signal is out of the actual acceptance ranges, including the nulls, the chip rejects the data. receiver logic operation figure 4 is a block diagram showing the logic for each receiver. bit timing the arinc 429 specifcation defnes timing tolerances for received data according to table 7. table 7. arinc 429 receiver timing tolerances high speed low speed bit rate 100kbps 1% 12k - 14.5kbps pulse rise time 1.5 0.5s 10 5s pulse fall time 1.5 0.5s 10 5s pulse width 5s 5% 34.5 to 41.7s
hi-3596, hi-3597, hi-3598, hi-3599 holt integrated circuits 7 the hi-359x family accept signals within these toler - ances and rejects signals outside these tolerances. receiver logic achieves this as described below: 1. an accurate 1mhz clock source is required to vali - date the receive signal timing. less than 0.1% error is recommended. 2. the receiver uses three separate 10-bit sampling shift registers for ones detection, zeros detection and null detection. when the input signal is within the differential voltage range for any shift registers state (one zero or null) sampling clocks a high bit into that register. when the receive signal is outside the differential voltage range defned for any shift register, a low bit is clocked. only one shift register can clock a high bit for any given sample. all three registers clock low bits if the differential input volt - age is between defned state voltage bands. valid data bits require at least three consecutive one or zero samples (three high bits) in the upper half of the ones or zeros sampling shift register, and at least three consecutive null samples (three high bits) in the lower half of the null sampling shift regis - ter within the data bit interval. a word gap null requires at least three consecutive null samples (three high bits) in the upper half of the null sampling shift register and at least three con - secutive null samples (three high bits) in the lower half of the null sampling shift register. this guaran - tees the minimum pulse width. fifo load control control bits cr2, cr6-8 / spi interface 32-bit shift register aclk bit counter and end of sequence 32nd bit data bit clock word gap bit clock end start sequence control error clock null zeros shift register ones eos label / decode compare 16-label memory 4 words x 32-bit fifo flag sck cs si so parity check shift register shift register error detection word gap timer figure 4. receiver block diagram
hi-3596, hi-3597, hi-3598, hi-3599 holt integrated circuits 8 3. to validate the receive data bit rate, each bit must follow its preceding bit by not less than 8 samples and not more than 12 samples. with exactly 1mhz input clock frequency, the acceptable data bit rates are shown in table 8. table 8. acceptable data bit rates at 1mhz input clock frequency high speed low speed data bit rate min 83kbps 10.4kbps data bit rate max 125kbps 15.6kbps 4. following the last data bit of a valid reception, the word gap timer samples the null shift register every 10 input clocks (every 80 clocks for low speed). if a null is present, the word gap counter is incre - mented. a word gap count of 3 enables the next reception. receiver parity if enabled by setting control register cr4 bit to 1, the receiver parity circuit counts ones received, including the parity bit. if the result is odd, then a 0 appears in the 32 nd bit. setting control register cr4 bit to 0 disables parity checking and all 32 bits are treated as data. retrieving data once 32 valid bits are recognized, the receiver logic generates an end of sequence (eos). depending on the state of control register bits cr2, cr6, cr7 and cr8, the received 32-bit arinc word is then checked for correct decoding and label match before it is loaded into the 4 x 32 receive fifo. arinc words that do not match required 9th and 10th arinc bit and do not have a label match are ignored and are not loaded into the receive fifo. table 9 describes this operation. table 9. fifo loading control cr2 arinc word matches enabled label cr6 arinc word bits 10, 9 match cr7, 8 fifo 0 x 0 x load fifo 1 no 0 x ignore data 1 yes 0 x load fifo 0 x 1 no ignore data 0 x 1 yes load fifo 1 yes 1 no ignore data 1 no 1 yes ignore data 1 no 1 no ignore data 1 yes 1 yes load fifo once a valid arinc word is loaded into the fifo, the eos signal clocks the data ready fip-fop to a 1, and the corresponding channels status register fifo empty bit (sr0- sr7) goes to a 0. the channels empty bit remains low until the corresponding receive fifo is empty. each received arinc word is retrieved via the spi interface using spi instruction n3 hex where n is the channel number 1-8 hex. up to 4 arinc words may be held in each channels receive fifo. the status register fifo full bit (sr8 - sr15) goes high when the corresponding channels receive fifo is full. failure to offoad a full receive fifo causes additional received valid arinc words to overwrite the last received word. label recognition the user loads the 16 byte label look-up table to spec - ify which 8-bit incoming arinc labels are captured by the receiver, and which are discarded. if fewer than 16 labels are required, spare label memory locations must be flled with duplicate copies of any valid label. after the look-up table is initialized, set channel control register bit cr2 to enable label recognition for that channel. if label recognition is enabled, the receiver compares the label in each new arinc word against the channels stored label look-up table. if a label match is found, the received word is processed. if no match occurs, the new arinc word is discarded and no indicators of received arinc data are presented. note that 00 hex is treated in the same way as any other label value. label memory bit signifcance is not changed by the status of control register bit cr9. the most signifcant label bit is always
hi-3596, hi-3597, hi-3598, hi-3599 holt integrated circuits 9 compared to the frst (msb) bit of each spi 8-bit data feld from spi instruction n1 hex, where n is the chan - nel number 1-8 hex. if a channel control register cr2 bit equals 0, the cor - responding receiver recognizes all label values as valid, as shown in table 9. reading the label memory the contents of each channels label memory may be read via the spi interface using instruction n2 hex where n equals the channel number 1-8 hex, as described in table 2. digital transmit function the transmit register can be used as a digital transmit - ter by connecting the tx1 and tx0 pins to an external arinc 429 line driver such as the hi-8570 or hi-8571 (except hi-3599). loopback self-test the hi-359x devices may use the transmit register to execute user-defned self-test sequences (loopback test) for each receiver. this feature may be individually enabled for each receiver by resetting control register cr5 bit to 0. a 32-bit test word is loaded to the trans - mit register using spi instructions n8 hex (for arinc 429 high-speed data rate) or n9 hex (for arinc 429 low speed). upon completion of the instruction, the word is shifted out of the register and routed to all receivers. if self-test mode is enabled and the receive channel is set to the correct speed, each channel will receive the test word as if it came from an external arinc 429 bus. if loopback is not enabled, the channel ignores the self-test word and continues to respond to the external arinc 429 bus ( note: in the case of hi-3597, rin1a and rin1b pins are not available). in all cases, the serial test word may be observed at the tx1 and tx0 pins (except hi-3599), as shown in table 10. note: the frst bit shifted into the self test register will be the frst bit sent to the receivers and the tx1 and tx0 pins. in arinc 429 protocol, this bit is the lsb. table 10. test outputs tx1 tx0 arinc 429 state 0 0 null 1 0 one 0 1 zero line receiver input pins the hi-3598 has two sets of line receiver input pins, rina/b and rina/b-40. only one pair may be used to connect to the arinc 429 bus. the rina/b pins may be connected directly to the arinc 429 bus. the rina/b-40 pins require an external 40k resistor to be added in series with each arinc input without affect - ing the arinc input thresholds. this option is especially useful in applications where lightning protection circuitry is also required. when using the rina/b-40 pins, each side of the arinc bus must be connected through a 40k series resistor in order for the chip to detect the correct arinc levels. the typical 10v differential signal is translated and input to a window comparator and latch. the comparator lev - els are set so that with the external 40k resistors, they are just below the standard 6.5v minimum arinc data threshold and just above the standard 2.5v maximum arinc null threshold. when using hi-3596, hi-3597 or hi-3599, only one set of arinc 429 receive inputs are provided for each chan - nel. the standard hi-3596, hi-3597 and hi-3599 use the direct-connection rina / rinb pins. the hi-3596-40, hi-3597-40 and hi-3599-40 devices use the rina-40 / rinb-40 pins and require external 40k series resis - tors. see the ordering information table for complete part number options. please refer to the holt an-300 application note for additional information and recommendations on light - ning protection of holt line drivers and line receivers. master reset (mr) assertion of master reset (mr) causes immediate ter - mination of data reception. the eight receive fifos are cleared. status register fifo fags and fifo status output signals are also cleared. master reset does not affect the eight channel control registers. master reset may be asserted using the mr input pin (hi-3596 and hi-3598 only) or by executing spi instruction n7 hex. an individual receive channel can be reset by setting its corresponding control register cr3 bit to 1. this clears the channels receiver logic and receive fifo and disables the receiver until cr3 is reset to 0. for applications requiring less than eight channels, unused receivers should be held in reset by setting the corre - sponding control register cr3 bits.
hi-3596, hi-3597, hi-3598, hi-3599 holt integrated circuits 10 timing diagrams serial input timing diagram chh t ceh t ces t ds t t dh cph t sckr t sckf t flag arinc data cs bit 31 rflg t spif t rxr t sck arinc word so si spi instruction n3 hex chz t hi impedance sckh t t dv cph t t sckl msb serial output timing diagram receiver operation bit 32 lsb hi impedance msb lsb cs sck so cs sck si figure 5. timing diagrams
hi-3596, hi-3597, hi-3598, hi-3599 holt integrated circuits 11 absolute maximum ratings supply voltages v dd ...................................................... -0.3 to +7.0v power dissipation at 25 o c plastic quad flat pack .......................... 1.5 w, derate 10mw/ o c voltage at pins rin1a, rin1b, rin2a, rin2b ........... -29v to +29v dc current drain per pin ........................................................ 10ma voltage at any other pin ......................................... -0.3v to v dd +0.3v storage temperature range ................................... -65 o c to +150 o c solder temperature (leads) ............................ 280 o c for 10 seconds (package) .................................................... 220 o c operating temperature range (industrial) ................ -40c to +85c (extended temp) .............. -55 o c to +125 o c note: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifcations is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics table 11. dc electrical characteristics v dd = 3.3v or 5.0v, gnd = 0v, t a = operating temperature range (unless otherwise stated) parameters symbol test conditions limits unit min typ max arinc inputs - pins rina, rinb, rina-40 (with external 40k), rinb-40 (with external 40k) differential input voltage (rin1a to rin1b, rin2a to rin2b, etc.) one zero null v ih v il v nul common mode voltages less than 30v with respect to gnd 6.5 -13.0 -2.5 10.0 -10.0 0 13.0 -6.5 2.5 v v v input resistance differential to gnd to v dd r i r g r h - - - 140 140 100 - - - k k k input current input sink input source i ih i il - -450 - - 200 - a a inpit capacitance (guaranteed but not tested) differential to gnd to v dd c i c g c h (rina to rinb) - - - - - - 20 20 20 pf pf pf logic inputs input voltage input voltage hi input voltage lo v ih v il 70% v dd - - - - 30% v dd v v input current input sink input source pull-down current (mr, si, sck, aclk pins) pull-up current ( cs ) i ih i il i pd i pu - -1.5 250 -600 - - - - 1.5 - 600 -250 a a a a logic outputs output voltage logic 1 output voltage logic 0 output voltage v oh v ol i oh = -100a i ol = 1.0ma 90% v dd - - - - 10% v dd v v
hi-3596, hi-3597, hi-3598, hi-3599 holt integrated circuits 12 parameters symbol test conditions limits unit min typ max output current (all outputs and bi- directional pins) output sink output source i oh i ol v out = 0.4v v out = v dd -0.4v 1.6 - - - - -1.0 ma ma output capacitance c o - 15 - pf operating voltage range v dd 3.15 - 5.25 v operating supply current i dd - 2.5 7.0 ma table 12. ac electrical characteristics vdd = 3.3v or 5.0v, gnd = 0v, t a = operating temperature range and f clk =1mhz 0.1% with 60/40 duty cycle parameters symbol limits units min typ max spi interface timing sck clock period t cyc 130 - - ns cs active after last sck rising edge t chh 25 - - ns cs setup time to frst sck rising edge t ces 10 - - ns cs hold time after last sck falling edge t ceh 10 - - ns cs inactive between spi instructions t cph 30 - - ns spi si data set-up time to sck rising edge t ds 10 - - ns spi si data hold time after sck rising edge t dh 30 - - ns sck rise time t sckr - - 10 ns sck fall time t sckf - - 10 ns sck high time t sckh 45 - - ns sck low time t sckl 25 - - ns so valid after sck falling edge t dv - - 65 ns so high-impedance after sck falling edge t chz - - 65 ns receiver timing delay - last bit of received arinc word to flag (full or empty) - hi speed delay - last bit of received arinc word to flag (full or empty) - lo speed t rflg t rflg - - - - 16 126 s s received data available to spi interface. flag to cs active t rxr 0 - - ns spi receiver read t spif - - 85 ns
hi-3596, hi-3597, hi-3598, hi-3599 holt integrated circuits 13 heat sink - chip scale package (qfn) only the hi-3596pcx, hi-3598pcx, and hi3599pcx use 44-pin or 64-pin plastic chip-scale (qfn) packages. these pack - ages have a metal heat sink pad on the bottom surface that is electrically connected to the die. for these receivers, small size is the primary advantage of this package style. heat sinking provides little beneft because power dissipation is low. if connected, the bottom heat sink pad should be connected to vdd. do not connect heat sink pad to gnd. additional pin / package configurations 64 - 55 - 54 - vdd 53 - 52 - flag 50 - rin8b-40 49 - hi-3598pci hi-3598pct 48 - rin8a-40 45 - rin7b-40 44 - rin7a-40 43 - rin7a 42 - 41 - rin6b 40 - rin6b-40 39 - 38 - rin6a-40 37 - rin6a 36 - rin5b 35 - rin5b-40 34 - rin5a-40 33 - rin5a - 17 rin2a - 19 rin2a-40 - 20 gnd - 27 - 32 - 1 - 2 aclk - 3 sck - 4 - 5 si - 6 so - 7 mr - 8 tx1 - 9 tx0 - 10 rin1a - 11 rin1a-40 - 12 rin1b-40 - 13 rin1b - 14 cs hi-3598pcx 64-pin plastic 9mm x 9mm chip-scale package (qfn) - 18 rin2b-40 - 21 rin2b - 22 rin3a - 23 rin3a-40 - 24 rin3b-40 - 25 rin3b - 26 rin4a - 28 rin4a-40 - 29 rin4b-40 - 30 rin4b - 31 47 - rin8a 46 - rin7b 51 - rin8b 56 - flag8 57 - flag7 58 - flag6 59 - flag5 60 - flag4 61 - flag3 62 - flag2 63 - flag1 - 15 - 16 aclk - 1 sck - 2 si - 4 so - 5 tx1 - 6 tx0 - 7 rin2a-40 - 8 rin2b-40 - 9 rin3a-40 - 10 rin3b-40 - 11 gnd - 12 cs - 3 24 - vdd 23 - flag 22 - rin8b-40 21 - rin8a-40 20 - rin7b-40 19 - rin7a-40 18 - rin6b-40 17 - rin6a-40 16 - rin5b-40 15 - rin5a-40 14 - rin4b-40 13 - rin4a-40 hi-3597 psi-40 & hi-3597 pst-40 24 - pin plastic small outline package (soic) hi-3597psx-40 44 - flag1 43 - flag2 42 - flag3 41 - flag4 40 - flag5 39 - flag6 38 - flag7 37 - flag8 36 - vdd 34 - rin8b 33 - 32 - rin8a 31 - 30 - rin7b 29 - rin7a 28 - rin6b 27 - rin6a 26 - rin5b 25 - rin5a 24 - 23 - - 12 - 13 rin2a - 14 gnd - 18 si - 4 so - 5 tx0 - 8 rin1a - 9 hi-3596pci hi-3596pct hi-3596pcx 44-pin plastic 7mm x 7mm chip-scale package (qfn) rin1b - 10 - 11 tx1 - 7 mr - 6 sck - 2 aclk - 1 rin2b - 15 rin3a - 16 rin3b - 17 rin4a - 19 rin4b - 20 - 21 - 22 35 - flag cs - 3 __ 44 - flag1 43 - flag2 42 - flag3 41 - flag4 40 - flag5 39 - flag6 38 - flag7 37 - flag8 36 - vdd 34 - rin8b-40 33 - 32 - rin8a-40 31 - 30 - rin7b-40 29 - rin7a-40 28 - rin6b-40 27 - rin6a-40 26 - rin5b-40 25 - rin5a-40 24 - 23 - - 12 - 13 rin2a-40 - 14 gnd - 18 si - 4 so - 5 tx0 - 8 rin1a-40 - 9 hi-3596pci-40 hi-3596pct-40 hi-3596pcx-40 44-pin plastic 7mm x 7mm chip-scale package (qfn) rin1b-40 - 10 - 11 tx1 - 7 mr - 6 sck - 2 aclk - 1 rin2b-40 - 15 rin3a-40 - 16 rin3b-40 - 17 rin4a-40 - 19 rin4b-40 - 20 - 21 - 22 35 - flag cs - 3 __
hi-3596, hi-3597, hi-3598, hi-3599 holt integrated circuits 14 aclk - 1 sck - 2 si - 4 so - 5 rin1a - 6 rin2a - 8 rin2b - 9 rin3a - 10 rin3b - 11 gnd - 12 cs - 3 24 - vdd 23 - flag 22 - rin8b 21 - rin8a 20 - rin7b 19 - rin7a 18 - rin6b 17 - rin6a 16 - rin5b 15 - rin5a 14 - rin4b 13 - rin4a hi-3599 psi & hi-3599 pst 24 - pin plastic small outline package (soic) rin1b - 7 hi-3599psx 44 - 43 - 42 - sck 41 - aclk 40 - 39 - vdd 38 - flag 37 - 36 - rin8b-40 34 - c s 33 - 32 - 31 - 30 - rin7b-40 29 - rin7a-40 28 - rin6b-40 27 - rin6a-40 26 - rin5b-40 25 - rin5a-40 24 - 23 - - 12 - 13 rin2a-40 - 14 gnd - 18 si - 4 so - 5 rin1a-40 - 8 rin1b-40 - 9 hi-3599pci-40 hi-3599pct-40 hi-3599pcx-40 44-pin plastic 7mm x 7mm chip-scale package (qfn) - 10 - 11 - 7 - 6 - 3 - 2 - 1 rin2b-40 - 15 rin3a-40 - 16 rin3b-40 - 17 rin4a-40 - 19 rin4b-40 - 20 - 21 - 22 35 - rin8a-40 aclk - 1 sck - 2 si - 4 so - 5 rin1a-40 - 6 rin2a-40 - 8 rin2b-40 - 9 rin3a-40 - 10 rin3b-40 - 11 gnd - 12 cs - 3 24 - vdd 23 - flag 22 - rin8b-40 21 - rin8a-40 20 - rin7b-40 19 - rin7a-40 18 - rin6b-40 17 - rin6a-40 16 - rin5b-40 15 - rin5a-40 14 - rin4b-40 13 - rin4a-40 hi-3599 psi-40 & hi-3599 pst-40 24 - pin plastic small outline package (soic) rin1b-40 - 7 hi-3599psx-40 44 - 43 - 42 - sck 41 - aclk 40 - 39 - vdd 38 - flag 37 - 36 - rin8b 34 - c s 33 - 32 - 31 - 30 - rin7b 29 - rin7a 28 - rin6b 27 - rin6a 26 - rin5b 25 - rin5a 24 - 23 - - 12 - 13 rin2a - 14 gnd - 18 si - 4 so - 5 rin1a - 8 rin1b - 9 hi-3599pci hi-3599pct hi-3599pcx 44-pin plastic 7mm x 7mm chip-scale package (qfn) - 10 - 11 - 7 - 6 - 3 - 2 - 1 rin2b - 15 rin3a - 16 rin3b - 17 rin4a - 19 rin4b - 20 - 21 - 22 35 - rin8a
hi-3596, hi-3597, hi-3598, hi-3599 holt integrated circuits 15 ordering information (hi-3598 all pins) ordering information (hi-3596 1 , hi-3597 2 & hi-3599) part number lead finish blank tin / lead (sn / pb) solder f 100% matte tin (pb-free, rohs compliant) part number temperature range flow burn in i -40 o c to +85 o c i no t -55 o c to +125 o c t no part number package description pc 64 pin plastic chip-scale package, qfn (64pcs) pq 52 pin plastic quad flat pack, pqfp (52ptqs) hi - 3598 xx x x part number input resistance blank 140k. direct connection to arinc 429 bus -40 100k. requires external 40k resistors part number lead finish blank tin / lead (sn / pb) solder f 100% matte tin (pb-free, rohs compliant) part number temperature range flow burn in i -40 o c to +85 o c i no t -55 o c to +125 o c t no part number package description pc 44 pin plastic chip-scale package, qfn (44pcs) ps 24 pin plastic wide soic, (24hw) part number digital transmit function 3596 1 yes 3597 2 yes 3599 no hi - 359 x xx x x - xx 1 not available in psx package. 2 not available in pcx package.
hi-3596, hi-3597, hi-3598, hi-3599 holt integrated circuits 16 revision history revision date description of change ds3598, rev. new 6/12/08 initial release. rev. a 5/22/09 clarifed relationship between spi bit order and arinc 429 bit order. rev. b 11/23/09 corrected typo on receivers pin nomenclature on page 3. added and updated figure and table cross-references. condensed control and status register tables. corrected minor typos. clarifed certain functional descriptions. added hi3596 & hi-3597 variants to datasheet. rev. c 01/18/12 correct typo in table 5. change cr11 to cr9
hi-3596, hi-3597, hi-3598, hi-3599 holt integrated circuits 17 package dimensions inches (millimeters) package type: 52ptqs detail a see detail a 0 7 .520 (13.2) bsc sq .394 (10.0) bsc sq .063 (1.6 ) typ .008 (.20) mi n .005 (.13 ) r m in r m in .005 (.13) .0256 (.65 ) bsc .015 .003 (.375 .075) .035 .006 (.88 .15) .055 .002 (1.4 .05) .063 (1.6) max. 52-pin plastic quad flat pack (pqfp) bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .354 (9.00) bsc .039 (1.00) max .008 (0.20) typ .0197 (0.50) bsc .010 (0.25) typ .016 .004 (0.40 ) .10 .281 .006 (7.15 ) .15 .281 .006 (7.15 ) .15 bottom view top view .354 (9.00) bsc 64-pin plastic chip-scale package (qfn) heat sink pad on bottom of package. heat sink must be left floating or connected to v dd . do not connect to gnd. inches (millimeters) package type: 64pcs bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95)
hi-3596, hi-3597, hi-3598, hi-3599 holt integrated circuits 18 24-pin plastic small outline (soic) - wb (wide body) .407 .013 (10.32 5 .32) .294 .002 (7.46 8 .051) 0 to 8 .0075 .0035 (.19 1 .089) .606 .004 (15.39 2 .102) .033 .017 (.83 8 .43) .095 .005 (2.41 3 .127) .0105 .0015 (.266 7 .038) see detail a detail a .050 (1.27) bsc .0165 .0035 (.41 9 .089) bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) inches (millimeters) package type: 24hw .20 3 .006 (5.15 .15) .016 .002 (0.40 .05) .010 (0.25) .020 (0.50) .008 (0.2) .039 (1.00) .276 (7.00) bsc .20 3 .006 (5.15 .15) typ typ bsc .276 (7.00) bsc ma x 44-pin plastic chip-scale package (qfn) inches (millimeters) package type: 44pcs bottom view top view heat sink pad on bottom of package. heat sink must be left floating or connected to v dd . do not connect to gnd. bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95)

▲Up To Search▲

Price & Availability of HI-3596PSIF-40

	To Download HI-3596PSIF-40 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .